The present invention relates to programmable logic devices, and more particularly to an improved programmable logic device employing electrically erasable memory cells and which may be programmed or reprogrammed while the device is installed in a user system.
Programmable logic devices (PLDs) provide a flexible logic function architecture, user-programmed through on-chip fuses or switches, to perform specific functions for a given application. PLDs can be purchased "off the shelf" like standard logic gates, but can be quickly custom tailored into a desired logic configuration.
To use PLDs, system designers draft equations describing how the hardware is to perform, and enter the equations into a PLD programming machine. The unprogrammed PLDs are inserted into the machine, which interprets the equations and provides appropriate signals to the device to blow the appropriate fuses or set the appropriate switches so that the PLD will perform the desired logic function in the user's system. The PLD typically includes thousands of the fuses or switches, arranged in a matrix to facilitate their manufacture and programming. Once programmed, the device is then removed from the programming machine and placed in its socket in the user's system to serve its final logic function. The programming and final logic functions are therefore separated, allowing the normal mode device pins to be multiplexed with programming mode functions to reduce or eliminate any pin overhead needed for programming the device.
While the PLDS on the market today enjoy substantial popularity with circuit designers, there are some applications in which it would be advantageous to have the capability to program the PLD while it is installed in the user's system, instead of only when in a programming machine.
Providing the ability to reconfigure a PLD "in-system" permits new applications for the devices that have not been possible before. One overhead for this flexibility is the addition of control pins necessary to reconfigure the device, since the normal device pins are occupied with their normal logic functions. Added pins result in added board space and less device packing per logic function.
It would therefore represent an advance in the art to provide a PLD which may be programmed in-system, and which employs non-volatile switch or memory elements to configure the device logic architecture.
It would further be advantageous to provide a PLD operable in a normal operating state and one or more utility states for reconfiguring the device, and wherein the device state is controlled by a state machine in dependence on external state control signals and the present state variables.
A further object of the invention is to provide an in-system PLD controlled by a state machine to minimize the number of required external pin connections needed for device reconfiguration.
Another object of the invention is to provide a PLD whose I/O pins can be isolated from the device AND and OR arrays during the utility states so that any signals driving these pins will not affect the device reconfiguration.
A further object of the invention is to provide a PLD whose outputs may be latched to a present valid data condition to preserve the output data during device configuration.
Yet another object of the invention is to provide a PLD whose outputs may be selectively latched to a valid data condition or tri-stated during a utility state.
A further object of the invention is to provide a PLD comprising electrically erasable and programmable cells and which includes on the device chip the circuit functions necessary for "in-system" programming of the cells.